WORLD 06 ATLAS · 8 DOMAINS · 24 SCENES · 1 CONCEPTS

The Infrastructure Reference — every cluster engineering concept.

An exhaustive taxonomy spanning silicon node layouts, lossless fabric topologies, direct-to-chip cooling, distributed checkpoint storage, gang schedulers, and FinOps unit economics.

GPU baseboards, NVLink switches, PCIe/CXL topologies, and HBM memory interfaces.

◈ SCENE

NVLink Mesh & NVSwitch Architecture

▲ COLLAPSE

Dedicated high-speed interconnect fabric within an 8-GPU baseboard.

900 GB/s to 3.6 TB/s bidirectional bandwidth per GPU connects all 8 devices in a non-blocking all-to-all topology.
Hardware-level memory load/store operations bypass standard OS driver queues.
Forms the scale-up domain for low-latency Tensor Parallelism (TP) and intra-node Pipeline Parallelism (PP).

OPEN SCENE EXHIBIT →

◈ SCENE

PCIe Gen5 vs CXL Host Bus Limits

▼ EXPAND

Host CPU-to-GPU transfer constraints, page locks, and memory coherency.

◈ SCENE

HBM3e Bandwidth & Roofline Knee

▼ EXPAND

The arithmetic intensity boundary between memory-bound and compute-bound execution.

◈ SCENE

HGX Server Baseboard Anatomy

▼ EXPAND

Structural layout of an enterprise 8-GPU scale-up training server.

▸ ENTRY

Unified Memory & Hardware Coherency

▼ EXPAND

Zero-copy pointer sharing and page fault migration across GPU and CPU address spaces.

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